The present invention relates to a method for computer aided design of layout design of a semiconductor integrated circuit.
Conventionally, semiconductor integrated circuits composed by integrating a plurality of transistor and wirings on a semiconductor substrate are designed using a CAD tool, as disclosed in Japanese Patent Application Laid Open Publication No. 2001-351985A, for example.
Recently, in association with miniaturization of semiconductor elements, a problem rises that transistor characteristics vary depending on a distance from a gate electrode of a transistor to an edge of a diffusion layer. In a P-channel MOS transistor having a long distance from the gate electrode of the transistor to the edge of the diffusion layer, an electric current decreases compared with other P-channel MOS transistors having the same gate width. On the other hand, in a N-channel MOS transistor having a short distance from the gate electrode of the transistor to the edge of the diffusion layer, an electric current decreases compared with other N-channel MOS transistors having the same gate width. Under the circumstances, if peripheral circuits, which are the same circuits to be layouted repeatedly depending on layout intervals of memory cells, are different from each other in the distance from the gate electrode of the transistor to the edge of the diffusion layer, circuit characteristics differ due to difference in the transistor characteristics of the peripheral circuits, resulting in invitation to inhibition of stable circuit operation.
The distance from the gate electrode of the transistor to the edge of the diffusion layer can be used as an index of a variation amount of a transistor characteristic in layout design. Conventional layout design systems for semiconductor integrated circuits, however, neither indicates the distance from the gate electrode of the transistor to the edge of the diffusion layer nor automatically generates a layout in which a variation amount of a transistor characteristic decreases. Under the circumstances, it is necessary for designers to set the distance from the gate electrode of the transistor to the edge of the diffusion layer by visual observation while taking account of a variation amount of an electric current as a transistor characteristic. This layout work is, however, not so easy and a desired layout cannot be obtained in some cases, reducing a design efficiency.
Further, variation amounts of transistor characteristics may differ depending on a manufacturing process, inviting design with erroneous distance set by a layout designer.